Compute providers are shifting their focus towards inference, with the realization that the AI industry requires more than just GPUs, as seen through the NVIDIA-Groq partnership. This has paved the way for a new collaboration between Intel and SambaNova.
Intel’s Xeon 6 CPUs to Serve as Host for Agentic Systems Supported by SambaNova’s SN50 Chip for Decoding
During this year’s GTC event, NVIDIA discussed the importance of disaggregated inference and the shift away from a ‘GPU-only’ approach towards incorporating newer forms of compute units into the infrastructure competition. With the introduction of SRAM-based LPUs in Rubin’s LPX racks through the Groq partnership, Intel and SambaNova have now revealed a new “inference architecture” featuring SambaNova’s RDUs and Intel’s Xeon 6 CPUs.
SambaNova has announced the latest stage of its collaboration with Intel, introducing a heterogeneous hardware solution combining GPUs for prefill, Intel® Xeon® 6 processors serving as both host and “action” CPUs, and SambaNova RDUs for decoding to deliver top-tier inference for demanding Agentic AI applications.
– SambaNova
This setup is designed to optimize RDUs for decoding tasks, with GPUs managing prefill activities and Xeon 6 CPUs handling orchestration and general-purpose work. The Intel-SambaNova partnership does not tie them to a specific hyperscaler for the GPU option, leaving room to integrate ASICs in this configuration. However, SambaNova has not provided detailed information on GPU-specific performance. SambaNova will incorporate their SN50 units, which will be discussed shortly, noting that they found Xeon 6 CPUs ideal for “end-to-end coding agent workflows” compared to ARM alternatives.
Let’s delve into the SN50 chip. Introduced in early 2026, this solution features SambaNova’s fifth-gen RDU units, incorporating DRAM, SRAM, and HBM onboard. The SN50 boasts 2TB of DDR5 memory, 64 GB HBM3, and 520 MB SRAM, aiming to deliver minimal latency, high throughput, and ample capacity with its unique memory architecture. According to the manufacturer, the DRAM + SRAM + HBM combination enables ‘agentic caching’.
Comparing Intel’s approach with SambaNova to NVIDIA’s strategy, Intel’s partnership appears to offer a more conservative option that does not require a substantial underlying infrastructure for disaggregated inference. For hyperscalers seeking a modular rack-scale solution focusing on “prefill + decode” tasks, the Intel-SambaNova collaboration presents a viable choice. While there were expectations for deeper RDU integration from Intel, it seems that, at least for now, the integration may be limited to the Xeon CPU acting as the host.
Intel’s CEO has joined SambaNova’s recent funding round, with Lip-Bu also being an early investor in the company. While there were discussions about Intel acquiring SambaNova, these plans were reportedly paused due to a board disagreement, leading Intel to opt for a funding role instead.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel.
Zuhair’s expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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