Up to 18x Smaller Textures

During GDC 2026, the Intel graphics engineer named Marissa du Bois took the stage to introduce Intel’s neural texture compression technology, which is similar to NVIDIA’s NTC in terms of being deterministic. This presentation served as a continuation of the R&D prototype showcased at GDC 2025, with the significant update being the transformation of Intel’s research into a standalone SDK.

Known as Texture Set Neural Compression (TSNC), this technology offers a more intelligent approach to storing game textures. Unlike traditional GPU block compression formats like BC1 through BC7, which use fixed rules to reduce texture size, TSNC capitalizes on training a small neural network through stochastic gradient descent to encode and decode specific textures in a given set. The outcome is a compact latent space representation that a small multi-layer perceptron can reconstruct at runtime into original data such as diffuse, normal, roughness, metallics, ambient occlusion, and emissive information.

The key concept behind TSNC’s compression method lies in the feature pyramid, which consists of four BC1-encoded latent-space textures arranged in various resolution configurations. Intel currently offers two variants with differing quality and compression trade-offs:

• Variant A utilizes two full-resolution latent images and two half-resolution ones. For 4K input textures, this translates to two 4K and two 2K latent images, totaling around 26.8 MB compared to the original 256 MB of uncompressed bitmaps. This results in over 9x compression, nearly double the 4.8x compression achieved by standard BC block formats alone. The perceptual quality loss, as measured by NVIDIA’s FLIP analysis tool, sits at approximately 5%, manifesting as minor precision loss in normal maps.
• Variant B, on the other hand, represents the more aggressive option. It downscales the latent images to 1/2, 1/4, and 1/8 of the original resolution, achieving over 17x compression, more than twice that of Variant A. However, the quality degradation is more pronounced, with BC1 block artifacts appearing in normal maps and AO/roughness channels, and a perceptual error of around 6–7%. While this may seem small in absolute terms, Intel acknowledges that it’s noticeable enough to viewers. Variant B is therefore best suited for distant or secondary materials where quality scrutiny is less likely.

Following last year’s R&D prototype, which was initially developed on PyTorch, the entire Texture Set Neural Compression compressor has been rebuilt using Slang compute shaders. Moreover, whether developers are working in Unreal, a custom engine, or performing decompression on the CPU, the same decompressor code can target the appropriate backend.

On the GPU side, Intel now supports Microsoft’s DirectX 12 Cooperative Vectors API, utilizing Intel Arc’s XMX matrix cores found on both A-series and B-series GPUs for hardware-accelerated matrix inference. For hardware lacking XMX support, a standard FMA (fused multiply-and-add) fallback is available for both CPUs and non-Intel GPUs.

Marissa du Bois from Intel detailed four distinct deployment strategies, each balancing disk space savings against memory usage:

• At install time — compress during shipping, decompress locally upon installation. Textures remain uncompressed on the user’s drive, mainly saving on distribution bandwidth.
• At load time — keep textures compressed on disk; decompression occurs into VRAM during game loading. This reduces both installation size and VRAM pressure during loading.
• At stream time — in conjunction with texture streaming, decompression happens on demand. This offers a balance between disk and memory savings but adds runtime inference load.
• At sample time — retain compressed textures in VRAM permanently and decode per-pixel in the shader. This represents the most aggressive option for VRAM reduction, with a constant inference cost.

Developers must choose a strategy based on their specific use case and underlying engine.

Intel conducted benchmarking for inference on a Panther Lake laptop using B390 integrated graphics at a full 1080p compute shader workload, yielding the following results:

• FMA path: 0.661 nanoseconds per pixel
• XMX linear algebra path: 0.194 nanoseconds per pixel

This showcases a 3.4x speedup from hardware-accelerated matrix math, with these numbers remaining consistent even on integrated graphics, making the sample-time deployment scenario more feasible than previously thought. For discrete GPUs, the overhead would be even lower. Intel plans to release an Alpha version of the Texture Set Neural Compression SDK later this year, followed by a beta and a public release, with exact dates yet to be determined.

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